View MB8508S064CE-100_2962955.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-11147-1e fujitsu semiconductor data sheet memory un-buffered 8 m 64 bit synchronous dynamic ram so-dimm MB8508S064CE-100/-100l 144-pin, 2 clock, 1-bank, based on 8 m 8 bit sdrams with spd n description the fujitsu mb8508s064ce is a fully decoded, cmos synchronous dynamic random access memory (sdram) module consisting of eight mb81f64842c devices which organized as two banks of 8 m 8 bits and a 2k-bit serial eeprom on a 144-pin glass-epoxy substrate. the mb8508s064ce features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb8508s064ce is optimized for those applications requiring high speed, high performance and large memory storage, and high density memory organizations. this module is ideally suited for workstations, pcs, laser printers, and other applications where a simple interface is needed. n product line & features parameter mb8508s064ce -100 -100l clock frequency 100 mhz max. burst mode cycle time 10 ns min. access time from clock 8.5 ns max. (cl = 3) operating current 680 ma max. power down mode current (i cc2p ) 16 ma max. 8 ma max. self refresh current (i cc6 ) 8 ma max. 4 ma max. ? unbuffered 144-pin so-dimm socket type (lead pitch: 0.8 mm) ? conformed to jedec standard (2 clk) ? organization: 8,388,608 words 64 bits ? memory: mb81f64842c (8 m 8, 4-bank) 8 pcs. ? 3.3 v 0.3 v supply voltage ? all input/output lvttl compatible ? 4096 refresh cycle every 65.6 ms ? auto and self refresh ? cke power down mode ? dqm byte masking (read/write) ? serial presence detect (spd) with serial eeprom: jedec standard spd format ? module size: 1.25 (height) 2.66 (length) 0.15 (thickness) ?cl-t rcd -t rp : 3-3-3 clk min. @100 mhz, 2-2-2 clk min. @66 mhz to top / lineup / index
MB8508S064CE-100/-100l 2 n pac k ag e 144-pin plastic so dimm (socket type) (mds-144p-p09) package and ordering information C 144-pin so-dimm, order as MB8508S064CE-100dg (dg = std. power ver., gold pad) -100ldg (ldg = low power ver., gold pad) to top / lineup / index
3 MB8508S064CE-100/-100l n pin assignments pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v ss 49 dq 13 97 dq 22 2v ss 50 dq 45 98 dq 54 3dq 0 51 dq 14 99 dq 23 4dq 32 52 dq 46 100 dq 55 5dq 1 53 dq 15 101 v cc 6dq 33 54 dq 47 102 v cc 7dq 2 55 v ss 103 a 6 8dq 34 56 v ss 104 a 7 9dq 3 57 n.c. 105 a 8 10 dq 35 58 n.c. 106 ba 0 11 v cc 59 n.c. 107 v ss 12 v cc 60 n.c. 108 v ss 13 dq 4 61 clk 0 109 a 9 14 dq 36 62 cke 0 110 ba 1 15 dq 5 63 v cc 111 a 10 16 dq 37 64 v cc 112 a 11 17 dq 6 65 ras 113 v cc 18 dq 38 66 cas 114 v cc 19 dq 7 67 we 115 dqmb 2 20 dq 39 68 n.c. 116 dqmb 6 21 v ss 69 cs 0 117 dqmb 3 22 v ss 70 n.c. 118 dqmb 7 23 dqmb 0 71 n.c. 119 v ss 24 dqmb 4 72 n.c. 120 v ss 25 dqmb 1 73 n.c. 121 dq 24 26 dqmb 5 74 clk 1 122 dq 56 27 v cc 75 v ss 123 dq 25 28 v cc 76 v ss 124 dq 57 29 a 0 77 n.c. 125 dq 26 30 a 3 78 n.c. 126 dq 58 31 a 1 79 n.c. 127 dq 27 32 a 4 80 n.c. 128 dq 59 33 a 2 81 v cc 129 v cc 34 a 5 82 v cc 130 v cc 35 v ss 83 dq 16 131 dq 28 36 v ss 84 dq 48 132 dq 60 37 dq 8 85 dq 17 133 dq 29 38 dq 40 86 dq 49 134 dq 61 39 dq 9 87 dq 18 135 dq 30 40 dq 41 88 dq 50 136 dq 62 41 dq 10 89 dq 19 137 dq 31 42 dq 42 90 dq 51 138 dq 63 43 dq 11 91 v ss 139 v ss 44 dq 43 92 v ss 140 v ss 45 v cc 93 dq 20 141 sda 46 v cc 94 dq 52 142 scl 47 dq 12 95 dq 21 143 v cc 48 dq 44 96 dq 53 144 v cc to top / lineup / index
MB8508S064CE-100/-100l 4 n pin descriptions symbol i/o function symbol i/o function a 0 to a 11 i address input cs 0 ichip select ba 0 , ba 1 i bank address dq 0 to dq 63 i/o data input/data output ras i row address strobe v cc power supply (+3.3 v) cas i column address strobe v ss ground (0 v) we i write enable n.c. no connection dqmb 0 to dqmb 7 i data (dq) mask scl i serial pd clock clk 0 , clk 1 i clock input sda i/o serial pd address/data input/output cke 0 i clock enable top view chip 0 chip 1 chip 2 chip 3 1143 31.75 mm 67.60 mm (mds-144p-p09) chip 4 chip 5 chip 6 chip 7 2144 59 60 61 62 to top / lineup / index
5 MB8508S064CE-100/-100l n serial-pd information note: any write operation must not be executed into the addresses of byte 0 to byte 127. some or all data stored into byte 0 to byte 127 may be broken. *1. sdram device attributes *2.checksum for bytes 0 to 62 this byte is the checksum for bytes 0 through 62. this byte contains the value of the low 8-bits of the arithmetic sum of bytes 0 through 62. byte function described hex value -100/100l 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 61 62 63 64 to 98 99 to 125 126 127 128+ defines number of bytes written into serial memory at module manufacture total number of bytes of spd memory device fundamental memory type number of row addresses number of column addresses number of module banks data width data width (continuation) interface type sdram cycle time (highest cas latency) sdram access from clock (highest cas latency) dimm configuration type refresh rate/type primary sdram width error checking sdram width minimum clock delay for back to back random column addresses burst lengths supported number of banks on each sdram device cas latency cs latency write latency sdram module attributes sdram device attributes sdram cycle time (2nd. highest cas latency) sdram access from clock (2nd. highest cas latency) sdram cycle time (3rd. highest cas latency) sdram access from clock (3rd. highest cas latency) precharge to activate min. (t rp ) row activate to row activate min. (t rrd ) ras to cas delay min. (t rcd ) activate to precharge minimum time (t ras ) module bank density unused storage locations spd data revision code checksum for byte 0 to 62 manufacturers information: unused storage vendor specific data: unused storage intel specification frequency intel specification details for 66 mh z support unused storage locations 128 byte 256 byte sdram 12 9 1 bank 64 bit +0 lvttl 10 ns 8.5 ns non-parity self, normal 8 0 1 cycle 1, 2, 4, 8, page 4 bank 2, 3 0 0 un-buffer *1 15 ns 9 ns no support no support 30 ns 20 ns 30 ns 60 ns 64 mbyte 1 *2 66 mh z cl=2, 3 80h 08h 04h 0ch 09h 01h 40h 00h 01h a0h 85h 00h 80h 08h 00h 01h 8fh 04h 06h 01h 01h 00h 0eh f0h 90h 00h 00h 1eh 14h 1eh 3ch 10h 00h 01h 57h 00h 00h 66h cfh bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tbd tbd upper v cc tolerance 0 = 10% lower v cc tolerance 0 = 10% supports write 1 /read burst supports precharge all supports auto- precharge supports early ras precharge 00001110 to top / lineup / index
MB8508S064CE-100/-100l 6 n block diagram clk 1 clk 0 add. ras cas we dqm 8 m 8 chip 0 cke cs clk dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqmb 0 add. ras cas we dqm 8 m 8 chip 1 cke cs dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dqmb 1 add. ras cas we dqm 8 m 8 chip 2 cke cs clk dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dqmb 2 add. ras cas we dqm 8 m 8 chip 3 cke cs dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dqmb 3 add. ras cas we dqm 8 m 8 chip 4 cke cs clk dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dqmb 4 add. ras cas we dqm 8 m 8 chip 5 cke cs dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dqmb 5 add. ras cas we dqm 8 m 8 chip 6 cke cs clk dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dqmb 6 add. ras cas we dqm 8 m 8 chip 7 cke cs dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dqmb 7 cke 0 cs 0 clk clk a 0 to a 11 , ba 0 , ba 1 ras cas we serial eeprom a 0 a 1 a 2 sda sda scl scl clk clk 10 w 10 w 10 w 10 w to top / lineup / index
7 MB8508S064CE-100/-100l n absolute maximum ratings (see warning) * : voltages referenced to v ss (= 0 v) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions *1. voltages referenced to v ss (= 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating conditionranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min. max. supply voltage* v cc C0.5 +4.6 v input voltage* v in C0.5 +4.6 v output voltage* v out C0.5 +4.6 v storage temperature t stg C55 +125 c power dissipation p d 8.0w output current (d.c.) i out C50 +50 ma parameter notes symbol value unit min. typ. max. supply voltage *1 v cc 3.0 3.3 3.6 v v ss 000v input high voltage, all inputs *1, 2 v ih 2.0 v cc +0.5 v input low voltage, all inputs *1, 3 v il C0.5 0.8 v ambient temperature t a 0+70 c *3. undershoot limit: v il (min) 4.6 v v ih v il pulse width 5 ns *2. overshoot limit: v ih (max) 50% of pulse amplitude v ih v il C 1.5v pulse width measured at 50% of pulse amplitude. = 4.6 v for pulse width <= 5 ns acceptable, = v ss C1.5 v for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude pulse width 5 ns v ih min v il max to top / lineup / index
MB8508S064CE-100/-100l 8 n capacitance (v cc = +3.3 v, f = 1 mhz, t a = +25 c) parameter symbol value unit min. max. input capacitance a 0 to a 11 , ba 0 , ba 1 c in1 48pf ras , cas , we c in2 42pf cs 0 c in3 49pf cke 0 c in4 40pf clk 0 , clk 1 c in5 32pf dqmb 0 to dqmb 7 c in6 13pf scl c scl 6pf input/output capacitance sda c sda 7pf dq 0 to dq 63 c dq 10pf to top / lineup / index
9 MB8508S064CE-100/-100l n dc characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2 (continued) parameter notes symbol condition value unit min. max. std. ver. low ver. operating current (average power supply current) *3 i cc1s burst: length = 1 t rc = min for bl = 1 t ck = min one bank active, outputs open addresses changed up to 1-time during t ck (min.) 0 v v in v il (max.) v ih (min.) v in v cc 680ma precharge standby current (power supply current) *3 i cc2p cke = v il , all banks idle t ck = min, power down mode 0 v v in v il (max.) v ih (min.) v in v cc 16 8ma i cc2ps cke = v il , all banks idle clk = h or l, power down mode 0 v v in v il (max.) v ih (min.) v in v cc 8 4ma i cc2n cke = v ih , all banks idle, t ck = min nop commands only, input signals (except to cmd) are changed 1-time during 3 clock cycles 0 v v in v il (max.) v ih (min.) v in v cc 80ma i cc2ns cke = v ih , all banks idle clk = h or l, input signal are stable 0 v v in v il (max.) v ih (min.) v in v cc 16ma active standby current (power supply current) *3 i cc3p cke = v il , any bank active t ck = min. 0 v v in v il (max.) v ih (min.) v in v cc 16 8ma i cc3ps cke = v il , any bank active clk = h or l 0 v v in v il (max.) v ih (min.) v in v cc 8 4ma i cc3n cke = v ih , any bank active t ck = min., nop commands only, input signals (except to cmd) are changed 1-time during 3 clock cycles 0 v v in v il (max.) v ih (min.) v in v cc 120ma i cc3ns cke = v ih , any bank active clk = h or l 0 v v in v il (max.) v ih (min.) v in v cc 16ma to top / lineup / index
MB8508S064CE-100/-100l 10 (continued) notes: *1. an initial pause (desl on nop) of 200 m s is required after power-on followed by a minimum of eight auto-refresh cycles. *2. dc characteristics is the serial pd standby state (v in = v ss or v cc ). *3. i cc depends on the output termination, load conditions, clock cycle rate and signal clock rate. the specified values are obtained with the output open and no termination register. *4. voltages referenced to v ss = v ssq (= 0 v). parameter notes symbol condition value unit min. max. std. ver. low ver. burst mode current (average power supply current) *3 i cc4 t ck = min, burst length = 4 outputs open, all banks active gapless data 0 v v in v il (max.) v ih (min.) v in v cc 480ma auto-refresh current (average power supply current) *3 i cc5 auto refresh t ck = min t rc = min 0 v v in v il (max.) v ih (min.) v in v cc 1360 ma self-refresh current (average power supply current) *3 i cc6 self-refresh t ck = min. cke 0.2 v 0 v v in v il (max.) v ih (min.) v in v cc 8 4ma input leakage current (all inputs) i i (l) 0 v v in v cc all other pins not under test = 0 v C30 30 m a output leakage current i o (l) 0 v v in v cc output is disabled (hi-z) C5 5 m a lvttl output high voltage *4 v oh i oh = C2.0 ma 2.4 v lvttl output low voltage *4 v ol i ol = +2.0 ma 0.4 v to top / lineup / index
11 MB8508S064CE-100/-100l n ac characteristics (1) base characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (2) base values for clock count/latency no. parameter notes symbol mb8508s064ce -100/100l unit min. max. 1clock period cl = 3 t ck3 10 ns cl = 2 t ck2 15 ns 2clock high time t ch 3.5 ns 3clock low time t cl 3.5 ns 4 input setup time t si 3ns 5 input hold time t hi 1ns 6 output valid from clock (t clk = min) *4, *5 cl = 3 t ac3 8.5 ns cl = 2 t ac2 9 7 output in low-z *6 t lz 0ns 8 output in high-z *6 cl = 3 t hz3 38.5ns cl = 2 t hz2 39ns 9 output hold time *6 t oh 3ns 10 time between refresh t ref 65.6 ms 11 transition time t t 0.5 2 ns 12 cke setup time for power down exit time t cksp 3ns no. parameter notes symbol mb8508s064ce -100/100l unit min. max. 1ras cycle time *7 t rc 90 ns 2ras precharge time t rp 30 ns 3ras active time t ras 60 110000 ns 4ras to cas delay time *8 t rcd 30 ns 5write recovery time t wr 10 ns 6ras to ras bank active delay time t rrd 20 ns 7 data-in to precharge lead time t dpl 10 ns 8 data-in to active/refresh command period cl = 3 t dal3 2 cyc + t rp ns cl = 2 t dal2 1 cyc + t rp ns 9 mode register set cycle time t rsc 20 ns to top / lineup / index
MB8508S064CE-100/-100l 12 (3) clock count formula (*9) (4) latency (the latency values on these parameters are fixed regardless of clock period.) notes: *1. an initial pause (desl on nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. *2. 1.4 v or v ref is the reference level for measuring timing of signals. transition times are measured between v ih (min) and v il (max). *3. ac characteristics assume t t = 1 ns and 50 pf of capacitive load. *4. maximum value of cl = 2 depends on t ck. *5. t ac also specifies the access time at burst mode except for first access. *6. specified where output buffer is no longer driven. t oh , t lz , and t hz define the times at which the output level achieves 200 mv. *7. actual clock count of t rc (i rc ) will be sum of clock count of t ras (i ras ) and t rp (i rp ). *8. operation within the t rcd (min) ensures that access time is determined by t rcd (min) + t ac (max); if t rcd is greater than the specified t rcd (min), access time is determined by t ac . *9. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *source: see mb81f64842c data sheet for details on the electrical. no. parameter symbol mb8508s064ce -100/100l unit 1 cke to clock disable i cke 1cycle 2 dqm to output in high-z i dqz 2cycle 3 dqm to input data delay i dqd 0cycle 4 last output to write command delay i owd 2cycle 5 write command to input data delay i dwd 0cycle 6 precharge to output in high-z delay cl = 3 i roh3 3cycle cl = 2 i roh2 2cycle 7 burst stop command to output in high-z delay cl = 3 i bsh3 3cycle cl = 2 i bsh2 2cycle 8cas to cas delay (min) i ccd 1cycle 9cas bank delay (min) i cbd 1cycle clock 3 base value clock period (round off a whole number) to top / lineup / index
13 MB8508S064CE-100/-100l n ac operating test condition (example of ac test load circuit) i/o z = 50 w 50 w 1.4 v 50 pf to top / lineup / index
MB8508S064CE-100/-100l 14 n serial presence detect(spd) function 1. pin descriptions scl (serial clock) scl input is used to clock all data input/output of spd sda (serial data) sda is a common pin used for all data input/output of spd. the sda pull-up resistor is required due to the open-drain output. sa 0 , sa 1 , sa 2 (address) address inputs are used to set the least significant three bits of the eight bits slave address. the address inputs must be fixed to select a particular module and the fixed address of each module must be different each other. for this module, any address inputs are not required because all addresses (sa 0 , sa 1 , sa 2 ) are driven to v ss on the module. 2. spd operations clock and data convention data states on the sda can change only during scl = low. sda state changes during scl = high are indicated start and stop conditions. refer to fig. 1 below. start condition all commands are preceded by a start condition, which is a transition of sda state from high to low when scl = high. spd will not respond to any command until this condition has been met. stop condition all read or write operation must be terminated by a stop condition, which is a transition of sda state from low to high when scl = high. the stop condition is also used to make the spd into the state of standby power mode after a read sequence. start fig. 1 C start and stop conditions stop scl sda start = high to low transition of sda state when scl is high stop = low to high transition of sda state when scl is high to top / lineup / index
15 MB8508S064CE-100/-100l acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will put the sda line to low in order to acknowledge that it received the eight bits of data. the spd will respond with an acknowledge when it received the start condition followed by slave address issued by master. in the read operation, the spd will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is issued by master, the spd will continue to transmit data. if an acknowledge is not detected, the spd will terminated further data transmissions. the master must then issue a stop condition to return the spd to the standby power mode. in the write operation, upon receipt of eight bits of data the spd will respond with an acknowledge, and await the next eight bits of data, again responding with an acknowledge until the stop condition is issued by master. slave address addressing following a start condition, the master must output the eight bits slave address. the most significant four bits of the slave address are device type identifier. for the spd this is fixed as 1010[b]. refer to the fig. 2 below. the next three significant bits are used to select a particular device. a system could have up to eight spd devices namely up to eight modules on the bus. the eight addresses for eight spd devices are defined by the state of the sa 0 , sa 1 and sa 2 inputs. for this module, the three bits are fixed as 000[b] because all addresses are driven to v ss on the module. therefore, no address inputs are required. the last bit of the slave address defines the operation to be performed. when r/w bit is 1, a read operation is selected, when r/w bit is 0, a write operation is selected. following the start condition, the spd monitors the sda line comparing the slave address being transmitted with its slave address (device type and state of sa 0 , sa 1 , and sa 2 inputs). upon a correct compare the spd outputs an acknowledge on the sda line. depending on the state of the r/w bit, the spd will execute a read or write operation. 1 0 1 0 r/w sa 2 sa 1 sa 0 device type identifier device address fig. 2 C slave address to top / lineup / index
MB8508S064CE-100/-100l 16 3. read operations current address read internally the spd contains an address counter that maintains the address of the last data accessed, incremented by one. therefore, if the last access (either a read or write operation) was to address(n), the next read operation would access data from address(n+1). upon receipt of the slave address with the r/w bit = 1, the spd issues an acknowledge and transmits the eight bits of data during the next eight clock cycles. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 3 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit = 1, the master must first perform a dummy write operation on the spd. the master issues the start condition, and the slave address followed by the word address. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/ w bit = 1. this will be followed by an acknowledge from the spd and then by the eight bits of data. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 4 for the sequence of address, acknowledge and data transfer. fig. 3 C current address read s t o p data a c k slave address s t a r t bus activity : master sda line bus activity : spd fig. 4 C random read s t o p data a c k slave address a c k a c k slave address word address s t a r t s t a r t bus activity : master sda line bus activity : spd to top / lineup / index
17 MB8508S064CE-100/-100l sequential read sequential read can be initiated as either a current address read or random read. the first data are transmitted as with the other read mode, however, the master now responds with an acknowledge, indicating it requires additional data. the spd continues to output data for each acknowledge received. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to fig. 5 for the sequence of address, acknowledge and data transfer. the data output is sequential, with the data from address(n) followed by the data from address(n+1). the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 255), the counter rolls over to address0 and the spd continues to output data for each acknowledge received. 4. dc characteristics note: *1. referenced to v ss . parameter note symbol condition value unit min. max. input leakage current s ili 0 v v in v cc C10 10 m a output leakage current s ilo 0 v v out v cc C10 10 m a output low voltage *1 s vol i ol = 3.0 ma 0.4 v fig. 5 C sequential read s t o p a c k a c k a c k data (n+x) data (n+2) data (n+1) data (n) slave address a c k bus activity : master sda line bus activity : spd to top / lineup / index
MB8508S064CE-100/-100l 18 5. ac characteristics no. parameter symbol value unit min. max. 1 scl clock frequency f scl 100 khz 2 noise suppression time constant at scl, sda inputs t i 100 ns 3 scl low to sda data out valid t aa 3.5 m s 4 time the bus must be free before a new transmission can start t buf 4.7 m s 5 start condition hold time t hd:sta 4.0 m s 6clock low period t low 4.7 m s 7 clock high period t high 4.0 m s 8 start condition setup time t su:sta 4.7 m s 9 data in hold time t hd:dat 0 m s 10 data in setup time t su:dat 250 ns 11 sda and scl rise time t r 1 m s 12 sda and scl fall time t f 300 ns 13 stop condition setup time t su:sto 4.7 m s 14 data out hold time t dh 100 ns 15 write cycle time t wr 15ms t f t high t low t r t hd : dat t su : dat t su : sto t aa t dh t buf t hd : sta scl sda (input) sda (output) t su : sta fig. 6 C timing waveform to top / lineup / index
19 MB8508S064CE-100/-100l n package dimension c 1997 fujitsu limited m144009sc-1-2 4.00?.10 (.157?004) 2.50?.10 (.098?004) 1.50?.10 (.059?004) 4.60?.13 (.181?005) details of "a" part details of "b" part 0.60?.05 (.024?002) 2.55(.100)min 0.25(.010)max 1 143 144 2 "a" "b" notches full r 4.00?.10 (.157?004) 20.00?.10 (.787?004) 67.60?.13(2.661?005) (.236?003) 6.00?.08 31.75?.13 (1.250?005) 2.10?.10 (.083?004) notches full r 1.80?.05 (.071?002) 3.30?.13 (.130?005) 23.20?.05 (.913?002) 24.50(.965)typ 29.00?.10 (1.142?004) 63.60?.10(2.504?004) 32.80?.05 (1.291?002) 2.10?.10 (.083?004) 4.60?.13 (.181?005) 0.80?.03 (.031?001) 23.20?.05 (.913?002) (.146?005) 3.70?.13 32.80?.05 (1.291?002) 3.80(.150)max 1.00?.10 (.039?004) 4.00(.157)min pin no.1 index dimension in mm (inches). 1 44-pin plastic so dimm (socket type) (mds-144p-p09) to top / lineup / index
MB8508S064CE-100/-100l 20 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9812 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. to top / lineup / index

▲Up To Search▲

Price & Availability of MB8508S064CE-100

	To Download MB8508S064CE-100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .